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MIPS

MIPS Instruction Field Layout

MIPS bit designations are always little-endian. For MIPS instructions , the layout of the bit fields within the instructions stays the same regardless of the endianess mode in which processor is executing. The MIPS architecture only uses Little-Endian bit ordering . Bit0 of an instruction is always the right-most bit within the instruction while bit […]

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MIPS – Memory access types

MIPS – Memory Access Types: MIPS system provide several memory access types. These are characteristic ways to use physical memory and caches to perform a memory access. The memory access type is identified by the Cacheability & Coherency Attribute (CCA) bits in the TLB entry for each mapped virtual page. The access type used for […]

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MIPS Components

Components of MIPS architecture: MIPS instruction Set Architecture:The MIPS 32& MIPS 64 Instruction Set Architecutre define a compatible family of instructions dealing with 32 bit of data and 64 bit of data (respectively) within the framework of the overall MIPS architecture. Included in ISA are all instructions, both priviledged & unprivildedged , by which the […]

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Cavium Multicore processor is based on the MIPS architecture. So while working on the card, I studied about the MIPS architecture and here are some to the basic architecture details about MIPS. There were some of the questions in mind when I started reading about MIPS. viz.. How MIPS architecture is superior to other architectures […]

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